Conventionally, second level interconnects according to the prior art are provided by way of solder balls. Second level interconnects include electrical interconnects provided between a package substrate having a die mounted thereon (hereinafter, a “package”), and a carrier such as the substrate of a circuit board. By “carrier,” what is thus meant herein is the next level substrate onto which the package is adapted to be mounted.
Typically, the prior art uses solder joints as the second level interconnects. To provide the solder joints, the prior art uses either solder balls or solder paste, which are then subjected to a reflow process, optionally involving thermal compression bonding. A solder resist layer may be disposed on the carrier, and the solder resist openings may be provided with flux prior to the solder ball placement process. The flux may be applied through a mask, or by way of a dip or spray process. Where solder paste is used, the paste may be applied by way of printing through a mask in a conventional manner. The package and the carrier thereafter undergo a reflow process at temperatures up to about 260 degrees Celsius. After solder joint formation, the first level interconnects may be supplied with an underfill material, such as with an epoxy material.
Disadvantageously, using solder joints for second level interconnects can among other things lead to cracked solder joints. As devices become smaller and thinner, thinner packages and smaller interconnect pitches are required. To accommodate such thinning, one option has been to reduce the package standoff with respect to the carrier using smaller solder balls or, as noted above, an LGA process where the solder paste for surface mount is the primary interconnect feature. However, smaller solder balls are hard to place, and present open/cold joint issues and or merged ball issues, especially as the size reduction of the package makes warpage of the package substrate a factor in the reliability of the second level interconnects. In addition, LGA joints also coplanarity issues, brought about mainly as a result of a warpage of the package substrate. Moreover, solder joints in general tend to crack as a result of stresses created by a number of factors including: differential thermal expansions between the substrate and the carrier; mechanical loading of the die; and flexure, drop or shock on the package.
In FIG. 1, a conventional microelectronic Assembly 100 is shown including a package 101 comprising a package substrate 102 supporting a die 104 thereon. The die 104 is shown as having been electrically and mechanically joined/bonded to the package substrate 102 by way of an array 106 of solder joints 108, and further by way of cured underfill material 110 as shown. An integrated heat spreader (IHS) lid 112 is further mounted onto package substrate 102 and thermally coupled to the die 104 by way of a thermal interface material (TIM) 114. Lid 112 is supported on the package substrate 102 by way of sealant 116. The package 101 is in turn supported on and electrically and mechanically bonded to a carrier 118, such as the substrate of a circuit board. Carrier 118 includes carrier lands 120 thereon adapted to allow an electrical connection of the carrier 118 to additional circuitry. In turn, package substrate 102 includes substrate lands 122 thereon adapted to allow an electrical connection of the package 201 to external circuitry. The lands 120 and/or 122 may include ENIG pads, for example. An array 124 of solder joints 126 is shown between the carrier lands 120 and the substrate lands 122, the solder joints 126 making up the second level interconnects. As seen in FIG. 1, a cracking of one or more of the solder joints 126 may occur as a result of the CTE mismatch between carrier 118 and the package 101.
The prior art fails to provide a reliable, cost-effective package substrate structure and method that address the disadvantages of second level interconnects including solder joints.
For simplicity and clarity of illustration, elements in the drawings have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Where considered appropriate, reference numerals have been repeated among the drawings to indicate corresponding or analogous elements.